R&D for Technologies for an Integrated Ultra-High Speed Network and Computer System

Masahiro Taka
Ultra-high Speed Network and Computer Technology Laboratories, Tokyo, Japan
taka@magical.egg.or.jp

The Ultra-high Speed Network and Computer Technology Laboratories were founded in March, 1994, in Tokyo, with the purpose of conducting research and development related to an integrated system involving gigabit networks and super computers. The specific objectives include developing network architecture, network access, information processing I/O channel control, and multi-dimensional image processing to provide a computer communication network system that will operate at gigabits/s. These key technologies for gigabit information infrastructure will make it possible to realize various applications of distributed information processing, such as real-time simulation of the natural environment and interactive visualization of scientific data computations.

The following four R&D subjects are identified for efficiently conducting the R&D.

(1) Gigabit network architecture and communication protocols

We are studying congestion control mechanisms in a gigabit network with a large bandwidth-delay product and the optimization of the protocol processing to improve the throughput. Another study is on packet scheduling techniques to support real-time continuous media applications which will exist together with traditional data applications in a high-bandwidth integrated environment.

Studies are also carried out on the resource reservation mechanisms for quality of service (QoS) control in an end-to-end network. A study is on a flexible bandwidth negotiation mechanism based on a scenario of media scaling applications. Also another study focuses on a mechanism for the resource reservation (such as CPU times) in an end-system for the application QoS guarantee.

(2) Architecture and protocol processing of gigabit access systems

To enable gigabit network interconnection, a study is carried out on gateway system architecture to match the faster operation of the intercommunicating processors .

The protocol processing in the gateway is currently executed by software, which will be a bottleneck for the faster operation of the gateway system. To solve this problem, a study is carried out on a protocol processing method and its circuit configuration that is based on a mixed architecture involving hardware and software processing.

The target for this study is to achieve a performance of several million packets per second for the interconnecting function.

(3) I/O channel control architecture and protocol processing

Based on the use of the fiber channel (FC) capable of transferring data at more than 8 Gbits/s on a single fiber, we are studying an I/O channel control technique that will convert data format between the FC and the ATM interface of a LAN or WAN in an efficient way.

To transfer the data of the multiple FC channels to remote end-systems via an IP over ATM network, the IP protocol should be implemented in the FC/ATM convertion. Therefore, we are also studying a high-throughput flow control method for the IP routing between the FC channels and ATM VCs.

(4) Highly efficient image data generation and transmission via gigabit networks

We are studying a highly-efficient image data generation and transmission techniques for multi-dimensional computer-graphics data of the order of tera bytes. This study focuses on methods of converting the original image data to a simplified description form by compressing unperceived parts of the image, and then transmitting them successively and preferentially. Also another study focuses on vector representation techniques to generate three-dimentional data in an efficient way.

Our target is to improve the performance of image data generation and transmission by a factor of ten compared to the present performance. The achievement of the improvement will allow real-time remote visualization via gigabit networks.

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Last updated 6 March 1997
James P.G. Sterbenz <jpgs@ieee.org>