SELECTED PUBLICATIONS

  1. ``Acceleration of atmospheric Cherenkov telescope signal processing to real-time speed with the Auto-Pipe design system,'' Proc. 3rd Workshop on Software Tools for MultiCore Systems (STMCS 2008), E. J. Tyson, J. Buckley, M.A. Franklin & R. D. Chamberlain, Submitted 2008.

  2. ``Sorting as a Streaming Application Executing on Chip Multiprocessors,'' Proc. Inter. Conf. on Parallel Architecture & Compilation Techniques (PACT 2008), R.D. Chamberlain, G.A. Galloway & M.A. Franklin, Submitted 2008.

  3. ``A Workload for Evaluating Deep Packet Inspection Architectures,'' Proc. IEEE Inter Symp. on Workload Characterization, M. Becchi, P. Crowley & M.A. Franklin, Submitted 2008.

  4. ``Simulation of Streaming Applications on Multicore Systems,'' Proc. 3rd Workshop on Software Tools for MultiCore Systems (STMCS 2008), S. Gayen, M.A. Franklin, E. J. Tyson & R. D. Chamberlain, April 2008.

  5. ``Application Development on Hybrid Systems,'' Proc. of ACM/IEEE Supercomputing Conf. (SC07), R.D. Chamberlain, E.J. Tyson, S. Gayen, M.A. Franklin, J. Buhler, P. Crowley & James Buckley, November 2007.

  6. ``Performance/Area Efficiency in Chip Multiprocessors with Micro-caches`,'' Proc. Conf. on Computing Frontiers (CF07), M. Becchi, M.A. Franklin & P. Crowley, May 2007.

  7. ``Biosequence Similarity Search on the Mercury System,'' Jrn'l of VLSI Signal Processing, 49(1):101-121, P. Krishnamurthy, J. Buhler, R.D. Chamberlain, M.A. Franklin, K. Gyang, A. Jacob & J. Lancaster, Oct. 2007.

  8. ``Automatic Deployment of Streaming Applications on Hybrid Architectures,'' Proc. of 11th High Performance Embedded Computing Workshop, R.D. Chamberlain & M.A. Franklin, Sept. 2007.

  9. ``A Federated Simulation Environment for Hybrid Systems,'' Proc. of 21st Int'l Workshop on Principles of Advanced & Distributed Simulation, pp. 198-207, S. Gayen, E.J. Tyson, M.A. Franklin & R.D. Chamberlain, June 2007.

  10. ``Exploiting Reconfigurability for Text Search,'' Presented at 10th High Performance Embedded Computing Workshop, R.D. Chamberlain, M.A. Franklin & R.S. Indeck, Sept. 2006.

  11. ``Impact of CMP Design on High-Performance Embedded Computing,'' Presented at 10th High Performance Embedded Computing Workshop, P. Crowley, M.A. Franklin,J. Buhler & R.D. Chamberlain, Sept. 2006.

  12. ``X-Sim: A Federated Heterogeneous Simulation Environment,'' Presented at 10th High Performance Embedded Computing Workshop, S. Gayen, E. Tyson, M.A. Franklin,R.D. Chamberlain & P. Crowley, Sept. 2006.

  13. ``Auto-Pipe and the X Language: A Pipeline Design Tool and Description Language,'' Proc. of Int'l Parallel and Distributed Processing Symp. (IPDPS06), E. Tyson, M.A. Franklin, J. Buckley, P. Crowley & J. Maschmeyer, April 2006.

  14. ``Accelerator Design for Protein Sequence HMM Search,'' Proc. Int'l Conf. on Supercomputing (ICS06), 288-296, R. Maddimsetty, J. Buhler, R. Chamberlain & M.A. Franklin, June 2006.

  15. ``Performance Models for Network Processor Design,'' IEEE Trans. On Parallel & Distributed Systems, V17, N6, T. Wolf & M.A. Franklin, June 2006.

  16. ``Application Development for Hybrid Pipelined Systems,'' Presented at 9th High Performance Embedded Computing Workshop, M.A. Franklin, P. Crowley, R. Chamberlain, J. Buhler & J. Buckley, Sept. 2005.

  17. ``VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance,'' Journal of VLSI Signal Processing, 40(1):57-72, R. Chamberlain, M.A. Franklin, P. Krishnamurthy & A. Mahajan, May 2005.

  18. "Network Processors: New Horizons," Chapter 1 Network Processor Design: Issues & Practices, Morgan-Kaufmann Pub., P. Crowley, M.A. Franklin, H. Hadimioglu & P. Onufryk, 2005 .

  19. ``Pipeline Task Scheduling on Network Processor,'' Chapter 11 Network Processor Design: Issues & Practices, Morgan-Kaufmann Pub. 2005, also in Proc. 3rd Workshop on Network Processors, S. Datar & M.A. Franklin, Feb. 2004.

  20. ``Network Processor Design: Issues and Practices, Volume 3'' Morgan Kaufmann Pub., Co-editors: P. Crowley, M.A. Franklin, H. Hadimioglu & P. Onufryk, 2005.

  21. ``SimplePipe: A Simulation Tool for Task Allocation & Design of Processor Pipelines with Application to Network Processors,'' in Proc. Symp. on Modeling, Analysis & Simulation of Computer & Telecommunications Systems \ (MASCOTS2004)}, Volendam, The Netherlands, M.A. Franklin & V. Joshi, Oct. 2004.

  22. ``Biosequence Similarity Search on the Mercury System,'' in Proc. IEEE 15th Inter. Conf. on Application-Specific Systems, Arch. & Processors, (ASAP '04), pp. 365-375, P. Krishnamurthy, J. Buhler, R. Chamberlain & M.A. Franklin, Sept 2004.

  23. ``An Architecture for Fast Processing of Large Unstructured Data Sets,'' Proc. Inter. Conf. on Computer Design (ICCD2004)}, San Jose, pp. 280-287, R. Chamberlain, M.A. Franklin, M. Hendrichs, B. Shands & J. White, Oct. 2004.

  24. ``Power Considerations in Network Processor Design,'' Network Processor Design - Issues & Practices: Volume II Morgan Kaufmann Pub., Sept. 2003 (Also in Proc. 2nd Workshop on Network Processor, ) M.A. Franklin & T. Wolf, Feb. 2003.

  25. ``The Mercury System: Exploiting Truly Fast Hardware for Data Search,'' Proc. of Int'l Workshop on Storage Network Architecture and Parallel I/Os, With R. Chamberlain, R. Cytron & R. Indeck, Sept. 2003.

  26. ``Network Processors: Emerging Themes and Issues,'' Chapter 1 Network Processor Design - Issues & Practices: Volume II, Morgan Kaufmann Pub., P. Crowley, M.A. Franklin, H.Hadimioglu & P. Onufryk, Sept. 2003.

  27. ``Dynamic Reconfiguration of an Optical Interconnect,'' Proc. of the 36th Annual Simulation Symp., P. Krishnamurthy, R.Chamberlain & M.A. Franklin, April 2003.

  28. ``Predictive Scheduling of Network Processors,'' Computer Networks, Elsevier Science Pub., T. Wolf, P. Pappu & M.A. Franklin, 2003.

  29. ``Dynamic Reconfiguration of an Optical Interconnect,'' Proc. 36th Annual Simulation Symposium, P. Krishnamurthy, R. Chamberlain & M.A. Franklin, April 2003.

  30. ``Gemini: An Optical Interconnection Network for Parallel Processing,'' IEEE Trans. on Parallel & Distributed Systems, 13(10):1038-1055, R. Chamberlain, C. Baw & M.A. Franklin, Oct. 2002.

  31. ``Network Processors: An Introduction to Design Issues,'' Chapter 1 Network Processor Design: Issues and Practices, Morgan Kaufmann Pub., R. Crowley, M.A. Franklin, H. Hadimioglu & P. Onufryk, Sept. 2002.

  32. ``Optical Network Reconfiguration for Signal Processing Appications,'' Proc. IEEE Inter. Conf. on Application-specific Systems, Architectures & Processors (ASAP 2002), San Jose, CA., July 2002, With R. Chamberlain & P. Krishnamurthy.

  33. ``Evaluating the Performance of Photonic Interconnection Network,'' Proc. 35th Annual Simulation Symp., San Diego, CA, April 2002, With R. Chamberlain, C. Baw, et.al.

  34. ``A Network Processor Performance and Design Model with Benchmark Parameterization,'' Network Processor Design: Issues & Practices, (also presented at Proc. 1st Workshop on Network Processors, Feb. 2002), Morgan Kaufamm Pub., Sept. 2002, With T.Wolf.

  35. ``Design Tradeoffs for Embedded Network Processors,'' Proc. Inter. Conf. on Architecture of Computing Systems (ARCS'02), Karlsruhe, Germany, April 2002, With T.Wolf.

  36. ``Tradeoffs Between Quality of Results & Resource Consumption in a Recognition System,'' in Proc. of the IEEE Inter. Conf. on Application-Specific Systems, Architectures \& Processors, July 2002, pp. 391-402, With M. DeVore, R. Chamberlain, G. Engel \& J. O'Sullivan.

  37. ``VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture \& Performance,'' Proc. (PDCS2001) Conf. on Parallel & Distributed Computing Systems Aug. 2001, With R. Chamberlain & A. Mahajan.

  38. ``Locality-Aware Predictive Scheduling of Network Processors,'' Proc. 2001 IEEE Inter. Symp. on Performance Analysis of Systems & Software; ISPASS 2001, Tucson, Arizona, Nov 2001, With T. Wolf.

  39. ``Performance Comparison of Parallel Finite Element & Monte Carlo Methods in Optical Tomography,'' Proc. 3rd Workshop on High Performance Scientific & Engineering Computing with Applications, Sept. 2001, Valencia, Spain, With S. Hendrata.

  40. ``Performance Evaluation of A Reconfigurable, Embedded Phtonic Multiring Interconnection Network ,'' Proc. 5th High Performance Embedded Computing Workshop (extended abstract), Sept. 2001, With R. Chamberlain & P. Krishnamurthy.

  41. ``Relationships Between Computational System Performance & Recognition System Performance,'' Proc. SPIE Symposium on AeroSense (Aerospace/Defense Sensing, Simulation & Controls), April 2001, With J. O'Sullivan, M. DeVore & R. Chamberlain.

  42. ``Dependence of Recognition Accuracy on Available Network Bandwidth.'' Proc. of 5th High Performance Embedded Computing Workshop, November 2001, With M.D. DeVore, J.A. O'Sullivan, R.D. Chamberlain).

  43. ``Distributed Deficit Round Robin Fairness Protocol for Channel Communications,'' Patent Submitted, Oct. 2000, With R. Chamberlain, A. Mahajan & C. Baw.

  44. ``Associative Memory Device,'' Patent Submitted, May 2000, With R. Indeck & R. Cytron.
  45. ``Analysis of computational System Performance in Automatic Target Recognition,'' Proc. 4th High Performance Embedded Computing Workshop (extended abstract), Sept. 2000, With J. O'Sullivan, M. DeVore & R. Chamberlain.

  46. ``Fairness Issues in an Embedded Photonic Ring Interconnect,'' Proc. 4th High Performance Embedded Computing Workshop (extended abstract), Sept. 2000, With A. Mahajan & R. Chamberlain.

  47. ``Parallel Implementations of 3D Synthetic-Focus Ultrasonic Image Generation,'' Proc. 9th IEEE Inter. Symp. on High Performance Dist. Comput., Nov. 2000, With A. Mahajan.

  48. ``CommBench- A Telecommunications Benchmark For Network Processors,'' Proc. IEEE Inter. Symp. on Performance Analysis of Systems & Software (ISPAS-2000), April 2000, With T. Wolf.

  49. ``Parallel Implementations of an Ultrasonic Image Generation Algorithm Using MPI,'' Proc. 11th Inter. Conf. on Parallel & Dist. Computing & Systems, , Nov. 1999, With A. Mahajan and M. Arthur.

  50. ``The Gemini Interconnect: Data Path Measurements & Performance Analysis,'' Proc. 6th Inter. Conf. on Parallel Interconnects (formerly MPPOI), Oct. 1999, With C. Baw and R. Chamberalin.

  51. ``Fair Scheduling in an Optical Interconnection Network,'' Proc. 7th Inter. Symp. on Modeling, Analysis and Simulation (MASCOTS '99), 56-65, Oct. 1999, With C. Baw and R. Chamberlain).

  52. ``Design of an Optically-Interconnected Multiprocessor,'' 5th Inter. Conf. on Massively Parallel Processing Using Optical Interconnections, MPPOI'98, 1998 With R. Chamberlain, R. Krchnavek and B. Baysal.

  53. ``Performance Optimization for Self-Timed Circuits,'' Proc. 8th Great Lakes Symp. on VLSI, Feb. 1998, With P. Prithvi.

  54. ``Simulation of Asynchronous Instruction Pipelines,'' Proc. 1996 Summer Computer Simulation Conf., July 1996, With C.-H. Chien.

  55. ``Application Load Imbalance on Parallel Processor,'' Inter. Parallel Processing Symp. (IPPS '96), April 1996, With V. Govindan.

  56. ``Simulation of Asynchronous Instruction Pipelines,'' Proc. 1996 Summer Computer Simulation Conf., July 1996, With C.-H. Chien.

  57. ``A General Matrix Iterative Model for Dynamic Load Balancing,'' Parallel Computing, Vol. 33, April 1996, With V. Govindan.

  58. ``Checkpointing in Distributed Systems,'' Jrnl. of Parallel & Distributed Systems, Vol. 35, No. 1, May 1996, With K. Wong.

  59. ``ARAS: Asynchronous RISC Architecture Simulator,'' Proc. 2nd Working Conf. on Asynchronous Design Methodologies, June 1995, London, England. With C-H Chien, T. Pan & P. Prabu.

  60. ``Genetic Epidemiology, Parallel Algorithms, and Workstation Networks,'' 28th Hawaii Inter. Conf. on Systems Sciences, Jan. 1995. With R. Chamberlain, G. Peterson and M. Province.

  61. ``Performance Comparison of Asynchronous Adders,'' Proc. IEEE Inter. Symp. on Advanced Research in Asynchronous Circuits & Systems, Nov. 1994. With T. Pan.

  62. ``Speculative Computation: Overcoming Communication Delays in Parallel Algorithms,'' Proc. 23rd Inter. Conf. on Parallel Processing (ICPP), Aug. 1994. With V. Govindan.

  63. ``Effects of Control Parameters on Dynamic Load Balancing,'' Proc. 8th Inter. Parallel Processing Symp., Cancun, Mexico, Apr. 1994. With V. Govindan.

  64. ``Distributed Computing Systems and Checkpointing,'' Proc. 2nd Inter. Symp. on High Performance Distributed Computing (HPDC-2), July 1993. With K. Wong.

  65. ``The N-body Problem: Distributed System Load Balancing & Performance Evaluation,'' Proc. 6th Inter. Conf. on Parallel & Distributed Processing, Oct. 1993. With V. Govindan.

  66. ``Clocked and Asynchronous Instruction Pipelines,'' Proc. 26th ACM/IEEE Inter. Symp. on Microarchitecture, Dec. 1993. With T. Pan.

  67. ``Performance Effects of Synchronization in Parallel Processors,'' Proc. 5th IEEE Symp on Parallel & Distributing Processing, Dallas, Texas, Nov. 1993. With R. Chamberlain.

  68. ``Parallel Simulated Annealing Using Speculative Computation,'' IEEE Trans. on Parallel & Distributed Computing,, 2, 4, pp.483-494, Oct. 1991. With E.E. Witte and R.D. Chamberlain.

  69. ``Optimum Buffer Circuits For Driving Long Uniform Lines,'' IEEE Jrnl. of Solid State Circuits , 26, 1, pp. 32-40, Jan. 1991, With S. Dhar.

  70. ``Analysis of Parallel Mixed-Mode Simulation Algorithms,'' Proc. Fifth Inter. Parallel Processing Symp. (IPPS), pp. 155-160. Apr. 1991, With R.D. Chamberlain.

  71. ``Hierarchical Discrete-Event Simulation on Hypercube Architectures,'' IEEE Micro, 10, 4, pp. 10-20, Aug. 1990. With R.D. Chamberlain.

  72. ``Task Assignment by Simulated Annealing,'' Proc. Inter. Conf. on Comp. Design (ICCAD90), pp. 74-77, Oct. 1990. With E. Witte and R. Chamberlain.

  73. ``Parallel Simulated Annealing Using Speculative Computation,'' Proc. 1990 Inter. Conf. on Parallel Processing (ICCP'90), pp. 286-290, Aug. 1990. With E. Witte and R. Chamberlain.

  74. ``Performance Analysis and Design of a Logic Simulation Machine,'' Jrnl. of Parallel and Distributed Comp., 7, pp. 416-440, Oct. 1989. With K. Wong.

  75. ``Discrete-Event Simulation on Hypercube Architectures,'' Proc. Inter. Conf. on Comp. Aided Design (ICCAD88), Nov. 1988. With R. Chamberlain.

  76. ``Performance Analysis and Design of a Logic Simulation Machine,'' Proc. 14th Inter. Symp. on Comp. Arch., pp. 46-55, June 1987. With K. Wong.

  77. ``Interconnection Networks: Physical Design and Performance Analysis,'' Jrnl. of Parallel and Distributed Comp., pp. 352-372, Nov. 1986. With S. Dhar.

  78. ``Collecting Data About Logic Simulation,'' IEEE Trans. on Computer-Aided Design, Vol. CAD-5, 2, pp. 405-412, July 1986. With R.D. Chamberlain.

  79. ``Statistics on Logic Simulation,'' Proc. 23rd Design Automation Conf., pp. 13-19, June 1986. With K.F. Wong, et.al.

  80. ``On Designing Interconnection Networks for Multiprocessors,'' Proc. 1986 Inter. Conf. on Parallel Processing, pp. 208-215, Aug. 1986. With S. Dhar.

  81. ``Two Strategies for Root Finding on Multiprocessor Systems,'' SIAM Jrnl. on Scientific and Statistical Comp., Vol. 6, No. 2, pp.314-333, April 1985. With I.N. Katz.

  82. ``Parallel Machines and Algorithms For Discrete Event Simulation,'' Proc. 1984 Inter. Conf. on Parallel Processing, pp. 448-458, Aug. 1984. With D. Wann and K. Wong.

  83. ``Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks,'' IEEE Trans. on Comp., C-32, 3, pp. 284-293, March 1983. With D. Wann.

  84. ``Timing Control of VLSI Based NLogN and Crossbar Networks,'' Proc. 1983 Inter. Conf. on Parallel Processing, pp. 59-64, Aug.1983. With S. Dhar and D. Wann.

  85. ``Pin Limitations and Partitioning of VLSI Interconnection Networks,'' IEEE Trans. on Comp., C-31, 11, Nov. 1982. With D. Wann and W. Thomas.

  86. ``Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks,'' Proc. 1982 Inter. Symp. Computer Arch. April 1982. With D. Wann.

  87. ``VLSI Performance Comparison of Banyan and Crossbar Communications Networks,'' IEEE Trans. on Comp., C-30, 4, April 1981.

  88. ``One Dimensional Optimization on Multiprocessor Systems,'' IEEE Trans. on Comp., C-30, 2, Feb.1981. With N. Soong.

  89. ``Pin Limitations and VLSI Interconnection Networks,'' Proc. 1981 Inter. Conf. on Parallel Processing, Aug. 1981. With D. Wann.

  90. ``VLSI Performance Comparison of Banyan and Crossbar Communications Networks,'' Proc. 1980 Workshop on Interconnection Networks for Parallel & Distributed Processing, Purdue Univ., April 1980.

  91. ``Design Issues in the Development of a Modular Multi-processor Communications Network,'' 1979 Int. Symp. on Comp. Architecture, April 1979. With S. Kahn.

  92. ``Working Set and Page Fault Frequency Paging Algorithms: A Performance Comparison,'' IEEE Trans. on Comp., C-27, 8, Aug., 1978. With R. Gupta.

  93. ``Parallel Solution of Ordinary Differential Equations,'' IEEE Trans. on Comp., C-27, 5, pp. 413-420, May 1978.

  94. ``Anomalies with Variable Partition Paging Algorithms,'' Comm. of the Assn. of Comp. Mach. (CACM), 21, 3, pp. 232-236, March 1978. With S. Graham and R. Gupta.