CSE/ESE 560M - Computer Systems Architecture I
The instructor for the course this semester is
My office hours are immediately after class, 4-5pm on MW, in Jolley 210.
The teaching assistants this semester are
Clayton Faber and Anthony Cabrera.
Their office hours are TBD.
Class lectures are generally from 2:30pm to 4pm on Mondays and
Wednesdays, in Lab Sciences room 250.
We will primarily use Piazza for communication in the class. Please use
Piazza over email for asking questions. The link for the class is TBD.
- Aug 28 Introduction
Lecture slides (including some added fab pictures),
- Aug 30 Instruction Set Architecture (ISA)
- Sep 4 Labor Day (no class)
- Sep 6 Instruction Set Architecture (ISA)
- Sep 11 Performance
- Sep 13 Pipelining
- Sep 18 Branch Prediction
- Sep 20 Technology
- Sep 25 Performance Modeling
- Sep 27 Superscalar
- Oct 2 Static Scheduling
- Oct 4 Caches
- Oct 9 Caches
- Oct 10 Caches
- Oct 16 Fall Break (no class)
- Oct 18 Dynamic Scheduling
- Oct 23 Review for Midterm Exam
- Oct 25 Midterm Exam
- Oct 30 Dynamic Scheduling
- Nov 1 Revisit Midterm Exam
- Nov 6 Dynamic Scheduling
- Nov 8 Multithreading
- Nov 13 Virtual Memory
- Nov 15 Virtual Memory
- Nov 20 Multicores
- Nov 22 Thanksgiving Break (no class)
- Nov 27 Multicores
- Nov 29 Multicores
- Dec 4 Multiprocessors
- Dec 6 Review for Final Exam
- Dec 11-13 Reading Period
- Dec 18 Final Exam (3:30-5:30pm)
The optional text for the course is Jean-Loup Baer, Microprocessor
Architecture: From Simple Pipelines to Chip Multiprocessors, Cambridge
University Press, 2010.
- Introduction - Baer, Section 1.1
- Performance - Baer, Sections 1.2-1.4 (except 1.3.2)
- Pipelining - Baer, Section 2.1
- Branch Prediction - Baer, Section 4.1
- Performance Modeling - Baer, Section 1.3.2
- Technology - Baer, Section 9.1
- Superscalar - Baer, Sections 3.1, 3.2, 3.5.1
- Static Scheduling - Baer, Sections 3.3.1-3.3.4, 7.5
- Caches - Baer, Sections 2.2, 6.1-6.3.1
- Dynamic Scheduling - Baer, Sections 5.0-5.2, 5.3.3, 5.4-5.5
- Multithreading - Baer, Section 8.1
- Virtual Memory - Baer, Sections 2.3, 6.1.1
- Multicores - Baer, Sections 7.0, 7.1.3, 7.2-7.4, 8.2
- Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta,
and John Hennessy,
"The directory-based cache coherence
protocol for the DASH multiprocessor,"
in Proc. of 17th ACM International Symposium on Computer Architecture
(ISCA), pp. 148-159, 1990, doi:10.1145/325164.325132
Last modified 20 Sep 2017.
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Roger Chamberlain <roger AT wustl.edu>