CSE/ESE 560M - Computer Systems Architecture I
The instructor for the course this semester is
My office hours are immediately after class, 4-5pm on MW, in Jolley 210.
The teaching assistants this semester are
Clayton Faber and Anthony Cabrera.
Their office hours are 1-2pm on MW and 4-5pm on TuTh.
They are both in Jolley 219, but if folks are visiting and asking questions,
they might move out into one of the collaboration spaces for more room,
so look around a bit if you don't see them at their desk.
Class lectures are generally from 2:30pm to 4pm on Mondays and
Wednesdays, in Lab Sciences room 250.
We will primarily use Piazza for communication in the class. Please use
Piazza over email for asking questions. The link for the class is
- Aug 28 Introduction
Lecture slides (including some added fab pictures),
- Aug 30 Instruction Set Architecture (ISA)
- Sep 4 Labor Day (no class)
- Sep 6 Instruction Set Architecture (ISA)
- Sep 11 Performance
- Sep 13 Pipelining
- Sep 18 Branch Prediction
- Sep 20 Technology
- Sep 25 Performance Modeling
- Sep 27 Superscalar
- Oct 2 Static Scheduling
sorry no video (the recording doesn't have any sound).
is from last fall. Ignore the logistics stuff up to the 7min timestamp, the
interesting lecture material starts right after that.
- Oct 4 Caches
sorry no video (again, the recording doesn't have any sound).
is from last fall. Start at timestamp 2min40sec.
- Oct 9 Caches
from last fall. Start at timestamp 6min20sec.
- Oct 11 Caches
from last fall. Start at timestamp 4min10sec.
- Oct 16 Fall Break (no class)
- Oct 18 Dynamic Scheduling
- Oct 23 Review for Midterm Exam
- Oct 25 Midterm Exam
- Oct 30 Dynamic Scheduling
- Nov 1 Dynamic Scheduling
- Nov 6 Revisit Midterm Exam (cancelled)
- Nov 8 Multithreading
- Nov 13 Virtual Memory
- Nov 15 Virtual Memory
- Nov 20 Multicores
- Nov 22 Thanksgiving Break (no class)
- Nov 27 Multicores
- Nov 29 Multicores
- Dec 4 Multiprocessors
- Dec 6 Review for Final Exam
- Dec 11-13 Reading Period
- Dec 18 Final Exam (3:30-5:30pm)
The optional text for the course is Jean-Loup Baer, Microprocessor
Architecture: From Simple Pipelines to Chip Multiprocessors, Cambridge
University Press, 2010.
- Introduction - Baer, Section 1.1
- Performance - Baer, Sections 1.2-1.4 (except 1.3.2)
- Pipelining - Baer, Section 2.1
- Branch Prediction - Baer, Section 4.1
- Technology - Baer, Section 9.1
- Performance Modeling - Baer, Section 1.3.2
- Learning gem5
- Tutorial video
- Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood, "The gem5 simulator," SIGARCH Comput. Archit. News 39(2):1-7, August 2011. DOI=10.1145/2024716.2024718.
- Superscalar - Baer, Sections 3.1, 3.2, 3.5.1
- Static Scheduling - Baer, Sections 3.3.1-3.3.4, 7.5
- Caches - Baer, Sections 2.2, 6.1-6.3.1
- Dynamic Scheduling - Baer, Sections 5.0-5.2, 5.3.3, 5.4-5.5
- Multithreading - Baer, Section 8.1
- Virtual Memory - Baer, Sections 2.3, 6.1.1
- Multicores - Baer, Sections 7.0, 7.1.3, 7.2-7.4, 8.2
- Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta,
and John Hennessy,
"The directory-based cache coherence
protocol for the DASH multiprocessor,"
in Proc. of 17th ACM International Symposium on Computer Architecture
(ISCA), pp. 148-159, 1990, doi:10.1145/325164.325132
- Practice Problem Set #1,
- Practice Problem Set #2,
- Practice Problem Set #3,
- Practice Problem Set #4,
- Practice Problem Set #5,
- Assignment #1, due Oct. 18, 2017.
- Practice Problem Set #6,
- Assignment #2, due Nov. 20, 2017.
- Practice Problem Set #7
Last modified 15 Nov 2017.
Return to Roger's home page.
Roger Chamberlain <roger AT wustl.edu>